CDC 6500

Mainframe   |  Introduced in 1967   |  Control Data Corporation (CDC)    « Back to Computer List
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During the Cold War, Control Data Corporation (CDC) provided the United States government with the fastest computers in the world.

Founded in 1957, CDC eventually excelled in three business areas: as a leading producer of disk drives and peripherals for the computer industry; as a data computer services provider; and as a pioneer of high-performance, multi-million dollar “supercomputers” used by defense-related government agencies and contractors. With chief engineer Seymour Cray, CDC released the CDC 6600 in 1964. The CDC 6600, created at Cray’s research lab in Chippewa Falls, WI, outperformed every computer available. It remained the fastest computer in the world until 1969 (when it was bested by another Cray-designed system, the CDC 7600). The CDC 6500 also marked the beginning of Seymour Cray’s twenty-year dominance over the small, but lucrative supercomputer industry.
 
The 6000-series set new benchmarks for performance, pioneered Cray’s parallel-processing architecture, and even introduced the first built-in liquid cooling system for a computer. Cray co-designed the 6600 with Jim Thorton, principal designer for the less-powerful (and less-expensive) CDC 6400. 1967 saw the release of the 6500 (designed by Bill Sembrat) which combined two central processing units (CPUs) from the 6400, and 10 peripheral processing units (PPUs) to handle data input and output.
 
Living Computers’ CDC 6500 was used at Purdue University from 1967 to 1989. It was acquired from the Chippewa Falls Museum of Industry and Technology in 2013, and underwent a painstaking, restoration lead by LCM+L principal engineer Bruce Sherry. To date, the team has dedicated more than 9,000 hours to restoring the system. Our CDC 6500 is also one of several systems available for remote online access.
One of a Kind
Usable System
Online Access
CDC 6500

Specifications

  • 60-bit word size, magnetic core memory, capacity of 128,000 words
  • 1000 nanosecond instruction cycle, 1.3 MIPS